RISC-V and Computing

Introduction of rISC v

RISC V a new next generation vision to the computing world. Yet, it has garnered serious international interest over the past 10+ years, since it was conceived by developers at the University of California Berkley in 2010. RISC-V (“risk-five”) is an instruction set architecture (ISA) rooted in reduced instruction set computer (RISC) principles. RISC-V is unique, even revolutionary, because it is a common, free, open-source ISA to which software can be ported, hardware can be developed, and processors can be built to support it.


The term RISC dates from about 1980. Before then, there was some knowledge that simpler computers can be effective (e.g., John Cocke at IBM Research), but the design principles were not widely described. Simple, effective computers have always been of academic interest, and resulted in the RISC instruction set DLX for the first edition of Computer Architecture: A Quantitative Approach in 1990 of which David Patterson was a co-author, and he later participated in the RISC-V origination. DLX was intended for educational use; academics and hobbyists implemented it using field-programmable gate arrays, but it was never truly intended for commercial deployment. ARM CPUs, versions 2 and earlier, had a public-domain instruction set and are still supported by the GNU Compiler Collection (GCC), a popular free-software compiler. Three open-source cores exist for this ISA, but were never manufactured. OpenRISC is an open-source ISA based on DLX, with associated RISC designs, and is fully supported with GCC and Linux implementations, although it too has few commercial implementations.

Software Support

RISC-V is supported by a number of language compilers, including the GNU Compiler Collection (GCC), a popular free-software compiler, and by the Linux operating system (both 32 and 64-bit).

Hardware Support

A number of companies are offering or have announced RISC-V hardware. These range from micro controllers to SOMs and SOCs that can run Linux, and FPGAs that can include a RISC-V core.

RISC V training

Developing RISC-V based CPU/IP Core

This course will cover detail steps how to implement soft-Core CPU/IP based on different FPGA platform. This will give inside about how to extends existing opensource IP corse.


This course initially introduce the bare metal application development on RISC-V platform with simple use cases. RTOS based solutions on RISC-V 32 or RISC-V 64 controllers u will be able to learn the FreeRTOS / PULP OS for developing real time application on RISC-V platform and able to exercise the different capabilities of the SoC/Corse like( sifive e core, GAP8, Soft-Core processor, shakti) watchdog, timers, SPI, I2C, UART, EEPROM, Splash etc. U will be working on different real time application and time critical features and implementing applications to interface ADCs, Sensors, Relay, Walls, Motor control.

RISC-V Assembler, Compiler and tool chain

This course will introduce RISC-V architecture and assembly language implementation. Initially GNU AS assembler implementation will be discussed. Also discussed on the different RISC-V ISA and extensions. Further in this course need of a RISC-V tool chain for different language,LLVM based compilers and working of different compiler will be discussed. Compiler optimization techniques and performance improvement with focused on RISC v specific implementation. With RISC-V Eco system and open source architecture, the demand for compiler experts has been grown in multi fold for migrating existing different language to RISC-V platforms and extends the tool chain capabilities with RISC-V extensions. The need of tool chain experts are grown drastically for RISC-V platform where thousands of companies innovation with different hardware acceleration, graphical acceleration, network acceleration , network/storage acceleration and other hardware driven faster way of achieving solution.

Embedded Linux and Device Drivers

RISC-V Eco system requires lot of embedded Linux development and open source contribution for developing/ migrating drivers for different IP Cores, Linux kernel features. The development of new features based on RISC-V hardware architecture and BSP migration is one of the major activities most of the RISC-V companies looking for. The expert programmers can go through this course to understand how to develop / migrate device drivers, develop new BSP framework, add new kernel features and work with existing RISC-V soft-core processor .

Embedded Linux basic and Product Development course

This course will cover basic Embedded Linux usage of cross compilation tool chain for Linux compilation, different RISC-V based distribution, application integration, application cross compilation, SDK migration, kernel file system optimization, boot loader compilation, image creation, and step-by-step guide on embedded product development. The kernel, drivers, device tree, and all the various software and decisions that need to be made when building a user space root file system, such as those in use in consumer electronics, military, medical, industrial, and auto industries. Hands-on labs with a RISC-V based emulated development target allow students to practice both coding and building the various parts of the system covered in class.

Embedded Linux Platform Development with Yocto Project

How to use different version of yocto project, how to create custom distribution from yocto, cross-compiler boot loaders, the kernel, drivers, device tree and root file system using yocto. How to use meta RISC-V layer, difference between recipes and layers, what is bit bake and its explanation, base bit bake classes in yocto, base poky layer in the yocto, extending yocto project with multiple meta layers, customizing yocto for production build and customizing yocto for CICD pipelines, generating patches for yocto, security.

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